High resolution pulse rate modulated digital-to-analog converter system

ABSTRACT

This disclosure relates to a pulse rate modulated digital-toanalog converter system which translates the digital information into a train of identical pulses, with the pulse rate proportional to the digital data. The pulse train produced by the encoder drives an analog switch, which in cooperation with a filtering analog circuit, converts the pulse train to an analogous DC voltage.

United States Patent Diaz et al. [4 1 Dec. 26, 1972 1 HIGH RESOLUTIONPULSE R 3,435,196 3/1969 Schmid .340/347 DA MQDULATED DIGITAL.T().ANALOG3,573,803 4/1971 Chatelon .340/347 DA 3,576,575 4/1971 Hellwarth..340/347 DA CONVERTER SYSTEM 3,497,625 2/1970 Hileman ..340/347 DA [72] Inventors: Richard A. Dlaz, Pittsburgh; Andras I. Subo, Export, bothof Pa. Primary Examiner-Maynard R. Wilbur Assistant Examiner.leremiahGlassman [73] Asslgnee' Ekcmc Carponflon Attorney-1 1-1. Henson, R. G.Brodahl and J. J.

Wood [22] Filed: Oct. 13, 1970 211 Appl. No.: 80,358 I [57] ABSTRACTThis disclosure relates to a pulse rate modulated digital-to-analogconverter system which translates the Elks}? digital information in atrainof identical pulses, with [58] Fieid v 40/347 DA 'the pulse rateproportional to the digital data. The "T pulse train produced by theencoder drives an analog switch, which in cooperation with a filteringanalog [56] References Cited circuit, converts the pulse train to ananalogous DC UNITED STATES PATENTS Vollage- 3,447,149 4 Claims, 6Drawing Figures 5/1969 Groth ..340/347 DA v PATENTEBBEB B I972 W EJLFBIJPpPPEIJIEL IrJFP. E [5 L E A %F&T HLJL. H|. JLALJL E FTEJL E EJLJLJLfiJL w v E HLEJL JIL HL JIL E 1|.v JL E m, Jl. J N; JI- R mu &

PATENIEBmzsmz 3,707,713

'snmsars DECIMALS L HIGH RESOLUTION PULSE RATE MODULATEDDIGITAL-TO-ANALOG CONVERTER SYSTEM BACKGROUND OF THE INVENTION 1. Fieldof the Invention This invention relates to a high resolution pulse ratemodulated digital-to-analog converter system.

2. Description of the Prior Art:

The direct typedigital-to-analog converter, converts directly fromdigital data intelligence into an analog voltage. In digital-to-analogconverters of this type, a common arrangement is the current summingnetwork. This technique requires the use of precision resistors withcarefully controlled tolerances. Another type of directdigital-to-analog converter is the R-2R ladder network which has thedistinct advantage that only two precise resistors need be selected. Theadvantages of both of these techniques reside in the fact that quickswitching is realized, and the output very rapidly settles down to asteady state value. This is particularly of advantage where speed is ofparamount importance such as encountered in many military applications.

The instant invention relates to the somewhat slower indirect type ofdigital-to-analog converter wherein the digital information is firstconverted into an intermediate encoded digital signal and then into a DCvoltage through an averaging process. This is known in the art as pulseduration or pulse width modulation technique. In those applicationswhere the speed is not quite as important, this slower system may beused with concomitant greater accuracy.

SUMMARY OF THE INVENTION In accordance with the instant invention meansare provided for generating intermediate encoded digital pulses whichare a function of binary digital data located in stored digitalintelligence means. Means are also provided for generating synchronizedpulses which are synchronized with the intermediate encoded digitalpulses, each pulse having a time width duration which is less than, andwholly contained within, the time width duration of the correspondingintermediate encoded digital pulse.

Means are provided for logically AND gating the intermediate encodeddigital and the synchronized pulses, to deliver a digital pulse trainoutput which is a function of the stored binary digits.

Finally, means arearranged for receiving and filtering the digital pulsetrain output to deliver an analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an illustrative electricalschematic of the high resolution pulse rate modulated digital-to-analogconverter system in accordance with the invention for handling four bitsof information;

FIGS. 2 and 3 are waveforms used in explairiing the operation of thecircuitry of FIG. 1;

FIG. 4 is a circuit diagram showing the basic encoder;

FIG. 5 is a series of waveforms used in explaining the operation of FIG.4; and

FIG. 6 is a nine-bit high resolution pulse rate modulateddigital-to-analog converter system in accordance with another embodimentof the invention.

DESCRIPTION OF EXEMPLARY' EMBODIMENT .The high-resolution pulse-ratemodulated digital-toanalog converter system in accordance with'thisinvention is illustrated in FIG. 1. In the interests of simplicity, thesystemis depicted using four hits of information, although it will beappreciated that the system can be expanded to include all the bitsrequired in a practical environment. The digital-to-analog convertersystem comprises, a basicencoder indicated generally at 10, andasynchronized pulse shaper circuitry indicated generally at 12. The basicencoder 10 comprises two component parts: (a) a commutator indicatedgenerally at 14, and (b) a pulse binary comparator indicated generallyat 16.

The. commutator 14 comprises four trigger flip-flops: TFFl, TFF2, TFF3,TFF4 and three AND gates, 18, 20, and 22. Each respective triggerflip-flop TFFl, TFF2, TFF3 and TFF4 receives the triggering pulse atterminal T, and has dual outputs identified as OandO. The Q output isthe complement of Q, i.e., when Q is a logic ONE,( is a logic ZERO andconversely.

The trigger flip-flops TFFl, TFF2, TFF3 and TFF4 function as a ripplecounter. It will be noted that the Q I output of TFFl is connected toprovide a trigger input pulse at T for TFF2, and it is also connected toprovide one input, identified as CI to an AND gate 24. The Q outputs ofTFF2 and TFF3 are connected to form the triggering input pulse to T forTFF3 and TFF4, respectively, and also as one input to the AND gates 18and 20, respectively. The last flip-flop TFF4 has its Qoutpui connectedat one input of the AND gate 22.

Q of TFFl is connected as one input to AND gates 18, 20 and 22respectively; similarly 60f TFF2 is connec ted as one input to AND gates20 and 22 respectively. Q oflFF3 is connected as one input to the ANDgate 22; Q of TFF4 is not utilized.

The pulse binary comparator 16 comprises four AND gates identified at24, 26, 28 and 30, the respective outputs of which are connected to alogic OR gate indicated at 32.

The commutator l4 outputs, which are identified at lines C1, C2, C3 andC4, provide one input to the AND gates 24, 26, 28 and 30, respectively;the other input to the AND gates 24, 26, 28 and 30 is provided from aregister indicated generally at 34. The register 34 comprises flip-flopsFF], FF2, FF3 and FF4, the O outputs of each flip-flop providing aninput to AND gates 24, 26, 28 and 30, respectively.

In the coding arrangement utilized, FFl contains the most significantbit (M88) and FF4 contains the lea significant bit (LSB).

The synchronized pulse shaper circuitry 12 comprises three JKflip-flops: FFS, FF6 and FF7; these flipflops have a trigger terminal atT, to which is applied pulses from a clock indicated symbolically at 36.The outputs of the flip-flops FFS, FF6 and FF7 are identified at Q Q1;Q2, 0,; and 0 :6,. The JK inputs of FFS are connected in common to asource of voltage +Vcc. The J K inputs of flip-flops FF6 and FF7 areconnected in common as shown; additionally the JK inputs of FF6 areconnected to the 0 output of FFS and to the input of an AND gate 38, andthe JK inputs of FF7 are connected to the output of the AND gate 38.

The AND gate 38 has two inputs, one of which is connected to Q, and theother of which is connected to Q as explained previously. Two logic NANDgates are identified at 40 and 42. As may be seen from the drawings thethree inputs to NAND gate 40 are Q Q, and Q hile the three inputs toNAND gate 42 are 0,, Q and For convenience in explaining the operationof the circuitry, the output of NAND gate 40 is identified at A, and theoutput of the NAND gate 42 is identified at B; the A and B outputs arethen fed to a NAND gate 44, the output of which is applied to a logicinverter 46. The output .of the logic inverter 46, identified as PS, isthen fed as one input to a logic AND gate 48, the other output of theAND gate 48 being derived from the output of the logic OR gate 32 of thebasicencoder l0.

OPERATION OF THE EMBODIMENT In order to appreciate the overall operationand the cooperation between the various component parts, reference willfirst be had to FIG. 4, which reproduces the basic encoder l0, and toFIG. which depicts various waveforms used in explaining the operation ofthe FIG. 4 circuitry.

The trigger flip-flops TFFl, TFF2, TFF3 and TFF4 constitutes a ripplecounter, the frequency of the clock pulses TP appearing at the firsttrigger terminal T of TFFl being successively divided in half as theoutput of one TFF provides the input to the succeeding TFF. The output Qof TFFI provides the pulse waveform identified at FIG. 5: Cl. TFF2, TFF3and TFF4 in cooperation with AND gates 18, and 22 provided the waveformsidentified in FIG. 5 at C C 'and C, respectively. An insight into thenature of this cooperation may be obtained from a consideration of TFFl,TFF2 and logic AND gate 18. The output of TFFl FIG. 5: Cl is also thetrigger input to TFF2, resulting in a pulse output at the 0 terminal ofTFF2, having a pulse width duration two times as great, and a frequencywhich is one half thg of its trigger input. The AND gate l8'has twoinputs: 0 (the complement of Q of TFFl) and the 0 output of TFF2. TheAND gate 18 will only have an output when both its inputs are HIGH(ONE). Thus, even though Q of TFF2 has a pulse width which is twice thatof C the AND gate 18 will only deliver an output for one half this pulsewidth (because the other input will be LOW), resulting in the outputdepicted at FIG. 5: C the pulse width of C, being exactly equal the timewidth of C v Similarly, by the same rotationale, the AND'gate 20 (whichhas three inputs) and the AND gate 22 (which has four inputs) cooperatewith the associated TFFs to produce the pulse waveforms depicted in FIG.5 at C and C, respectively. As may be seen from a study of FIG. 5, theCl pulse output is one-half that of the trigger signal TP (i.e., 16:8).Correspondingly, the C, output of AND gate 18 is one-half that of C1(i.e., 8:4), and in a similar manner C the output of AND gate 20, isone-half that of C (i.e., 4:2). Finally, C the output of AND gate 22 isone-half that of C (i.e., 2:1 More importantly it should be noted that'Cl provides a HIGH (OR ONE) input eight times to AND gate 24, Cprovides a HIGH input four times to AND gate 26, C, provides a HIGHinput twice to AND gate 28, and finally C, provides HIGH input once toAND gate 30.

The flip-flops of register 34 contains a digital ONE if their respectiveQ outputs are HIGH. Conversely, a digital ZERO is indicated by the LOWstate at the Q output terminal.

Whenever any of the AND gates 24, 26, 28 and.30 has both inputs HIGH,then that AND gate will deliver an input to the logic OR gate 32. Thegate 32 is a logic INCLUSIVE OR, so that whenever there is a HIGH(DIGITALONE) on any one or more of its inputs, it will deliver anoutput. A number of examples will serve to point up this operation. I

Assume by way of illustrating that the 84-2l binary code is beingutilized, and the flip-flops FFl, FF2,

FF3' and FF4 areset (by any convenient means not shown) to reflect thedesired intelligence.

' Assume first that the register 34 contains the decimal zero which incode form is 0000. This being the case, although the trigger flip-flops(TFFs) will provide a I-IIGH to the AND gates to the sequence: 8-4-2-1,there will be no output because the Q of the respective flip-flops FF],FF2, FF3 and FF4 will be LOW (ZERO). The result is that there will be nooutput from the OR gate 32. This is shown in FIG. 5 by the straight line(representing ground or a low potential) to the right of the decimal 0.

Assume now that the register 34 contains a decimal 3. In the 8421 codethis will be 0011; thus the Q outputs of FF3 and FF4 will be HIGH. TheC1 and C2 outputs will provide HIGH signals to the AND gates 24 and 26,eight and four times respectively, but no output will be delivered fromthe AND gates because the respective register 0 inputs are low (ZEROS).When the C3 output is applied to AND gate 28, pulses will be deliveredat 50 and 52; similarly, the single time that the C4 output is deliveredto AND gate 30, will result in the pulse output 54. The pulse trainoutput shown to the right of the decimal 3 in FIG. 5 will thenconstitute the output of the OR gate 32. The decimal 9 in 8421 code is1001. This results in the pulse waveform output shown to the right ofthe number 9 in FIG. 5. Again as the respective AND gates 24, 26, 28 and30 are interrogated in sequence, they will have an output if the Q ofthe flip-flop with which they are associated in HIGH. However, it willbe noted that, as indicated by the identification numeral 56, there issome merging of pulses and this can produce deleterious results. Thismerging of pulses results from the close proximity of the C1 and C4output pulse train. Finally, the decimal 15, which is coded 1111, willresult in a full continuous output from the OR gate 32 as shown in FIG.5. Note: the synchronized pulse shaper circuitry 12 eliminates the pulsemerging problem as will be explained presently.

Referring now back to FIGS. 1, 2 and 3, it will be noted that the clock36 provides a series of pulses which are applied to the JK flip-flopsFFS, FF6 and FF7; these together constitute a synchronous counter aswill be shown. The clock pulses are applied to the trigger terminal T ofeach JK flip-flops FFS, FF6 and v FF7. It will be recalledthat theoutput terminal 0 of FFS is connected to the .II( terminals of FF6 andto the AND gate 38. The output terminal 0, of FF6 is connected as aninput to the AND gate 38. The output of the AND gate 38 forms the JKinput to FF7.

The Q and Q outputs of the JK flip-flops are complemented. Each JKflip-flop can only change state when its JK input is HIGH (ONE) and theclock pulse is going from 1 to (high to low). The application of theclock pulse to the trigger terminals T then produces Qe pulse trainshown in FIG. 2 at: 0,, Q Q and 6,, Q, and Q The dynamics of theoperation of the JK flipflop may be appreciated from a study of thetable below. Note: 1-0 means the clock pulseis moving from high to low,(negative going), 0-] means it is moving from low to high (positivegoing), and 0-0, ll means that the pulse remains at the same low or highpotential for a time interval. The l.0(a) and l0(b) notation is utilizedto indicate the initial state of the J K input of the respectiveflip-flop when the trigger pulse isapplied, and when the trigger pulsehas completed its excursion from I to 0 respectively.

TABLE AND GATE 0 0;

As will be observed, the output of O is the TP input which is applied tothe commutator 14 of the baic e ncod1l0. The various outputs 0,, Q Q andQ Q and Q are applied to the NAND gates 40 and 42. The NAND gate 40performs the operation A Q Q similarly NAND gate 42 performs theoperation B Q Q2 Q3.

The NAND gate 40 has a low output A only when 0,, Q and 0 are high, thusproducing output pulses identified at 58, 60 and 62 respectively.Similarly, the N AND gat e 42 produces a low output B only when 61, Qand 0 are high thus producing output pulses identified at 64, 66 and 68.TB NAND gate 44 then performs the logic operation AB producing output70, 72, 74, which occur whenever there is an input signal on either A orB. Thus, the pulses 58 and 64 cooperate to form pulse 70. Similarlypulses 60 and 62 cooperate to form pulse 72, and finally pulses 62 and68 cooperate to form pulse 74. The pulses marked 70, 72 and 74 in FIG.2, are then inverted by the logic inverter 46 to produce the pulsesshown at 76, 78, 80; these pulses give a mark-space ratio of 3:1, thatis the mark is three times as long as the space.

It will be observed now froma study of FIG. 2, that the PS pulsesstraddle the TB pulses i.e., the T? pulses change in the middle of PS sothat any perturbations in rise and fall time of the T? pulses iseffectively excised.

As a result of this straddling technique, the merging of pulses (asoccurred at 56 in FIG. has now been effectively eliminated, so that ineffect, the merged pulse is split into three pulses 82, 84, 86 asindicated. It

should also be noted that each decimal is now represented by discretepulses; for example, decimal 14 is represented by 14 pulses, decimal 15by 15 pulses, etc.

DESCRIPTION OF SECOND EMBODIMENT For purposes of simplicity, the highresolution pulse rate modulated digital-to-analog converter system hasthus far been described in connection with only four bits ofinformation. In FIG. 6 there is shown a digitalto-analog system in apractical environment having an eight-bit register plus a sign bit. 7

Referring now to FIG. 6 the register 88 is arranged to handle eight bitsin addition to a sign bit (5.8). The lower bits in the register areidentified at 2, 2, 2 and 2 and the upper bits are indicated at 2, 2 2and 2. The lower bits are connected to a pulse binary'comparator 90, andthe upper bits are connected to a similar pulse binary comparator 92.

A clock 94 is applied to a synchronized pulse shaper circuit 96, whichin cooperation with a commutator 98 interrogates the pulse binarycomparators and 92.

The sign bit in the register 88 is connected to logic AND gates 100, 102and to a logic inverter 104, the output of the amplifying inverter 104being connected to logic AND gates 106 and 108. The outputs of AND gates100, 102, 106 and 108 are connected to analog switches 110, 112, 114 and116 respectively. The analog switches 110 and 112 are connected to apositive voltage reference +Vr, while the analog switches 114, 116 areconnected to a negative source of potential Vr. The output of the analogswitches 110, 112, 114 and 116 are applied through aresistive-capacitive network 118, 120, 122 and 124 respectively, and aswill be observed from the drawing the resistors have the magnitudes Rand 2 R. Capacitors (unidentified by number) are connected between themid-point of the resistors and ground to provide additional filtering.

The networks 118, 120, 122, 124 are connected in common to anoperational amplifier indicated generally at 126. The operationalamplifier has a feedback path with a resistor 128 and a capacitor 130 toprovide an averaging output at the terminal 132. Note the system canalsobe used in a binary coded decimal (BCD) digital-to-analog convertersystem. The resistive network has the magnitudes indicated because theinformation in the register is in binary form; had the information beenin BCD form the value of the resistors would have been 10R instead of 2R.

OPERATION OF THE SECOND EMBODIMENT In the field of the numerical controlof machine tools, the digital-to-analog converter system of the instantinvention finds particular utility. For example, it is desired tocontrol the rotational velocity of a d-c motor which responds only to ananalog voltage. A series of command signals, calculated by computer orpredetermined in advance, are arranged in binary coded form in theregister 88. The objective of the digital-to-analog converter systemthen will be to convert the coded signals to analog form at the output132 for application to the dc motor.

The register 88 contains provision for a sign bit. If the sign ispositive, AND gates 100 and 102 will receive an input, and if the othertwo inputs are present it will provide a pulse output train to therespective analog switches 110 and 112. Similarly, if the sign isnegative, it will be inverted by the logic inverter 104, to provide oneinput to AND gates 106 and 108, and if the other two inputs are presentwill pass a pulse train to the analog switch as 114 and 116.

The operation of the synchronized pulse shaper circuitry 96 thecomparator 90 and the pulse-binary comparator 90, 92 is exactly the sameas their counterparts described in connection with FIGS. 1 and 2. LogicAND gates 100, 102, 106 and 106 serve the same logic function as ANDgate 48 in FIG. 1.

A code number in the register 88 provides an appropriate pulse train asdepicted in FIG. 3 for the decimals +l5. Each time a pulse is applied toan analog switch, i.e., 110, 112, 114, or 116, the switch is closedconnecting a referencevolta'ge +Vr or -Vr to the operational amplifier126 which functions as a filter, which produces an output signal whichis proportional to the pulse rate. The greater the number of pulses thehigher the charge on the capacitor 130, and of course the higher theanalogvoltage produced at 132.

The response time of the system and the ripple content of the filteredoutput are closely related. The harmonic content of the ripple dependsupon the digital data. In general, the frequency of the lowest harmoniccomponent of the ripple waveform should be as high as possible in orderto mitigate filtering requirements. For this reason the outputs C C C Cof the commutator 98 are shared by two pulses binary comparators 90 and92; this means that the two comparators 90, 92 pass through the samesequence, but handle four different bits of input data.

The two pole filter is used in order to obtain the desired ripplereduction and to improve the settling time of the digital-to-analogconverter system.

It will therefore be apparent that there has been described a highresolution pulse rate modulated digital-to-analog converter systemhaving wide application for industrial use, particularly in the field ofthe numerical control of machine tools.

We claim as our invention: 1. A digital to analog converter systemcomprising: commutator means providing interrogating pulses in apredetermined sequence;

comparator means for comparing said interrogating pulses with binarydigital data located in stored digital intelligence means to ascertaincoincidence, and for delivering intermediate encoded digital pulseswhich are a function of said binary digital data;

synchronized counter means coupled with said comparator means to enablesynchronization;

logic circuitry means adapted to receive the output of said synchronizedcircuit means for logic operations thereon to provide synchronizedpulses which are synchronized with said intermediate encoded digitalpulses, each synchronized pulse having a time width duration which isless than and wholly contained within the time width duration of thecorresponding intermediate encoded digital V pulses;

means for logically AND gating said intermediate encoded digital andsynchronized pulses and delivering a digital pulse train output which isa function of said binary digital data;

analog switching means having on and off positions adapted to beselectively connected to positive or negative voltage sourcesrespectively, and operatively connected to said logic AND gating means,the digital pulse train output providing selective actuation ofsaid-analog switching means;

weighted resistor network means connected to said analog switchingmeans, and adapted to be selectively energized by said voltages throughsaid analog switching means;

operational amplifier means having a capacitor and a resistor connectedin parallel in the feedback path thereof, said operational amplifiermeans being coupled to such weighted resistor network means, the outputof said operational amplifier means delivering an analog signal.

2. A digital-to-analog converter system comprising:

means for generating intermediate encoded digital pulses which are afunction of binary digits located in stored digital intelligence means,comprising commutator means for providing interrogating pulses in apredetermined ordered sequence;

comparator means for comparing said interrogating pulses with saidbinary digits in said stored digital intelligence means to ascertaincoincidence, comprising first logic AND gating means, EXCLUSIVE ORgating means, said first logic AND gating means having one inputconnected to said binary digits and the other connected to receive saidinterrogating pulses, the outputs of said first logic AND gating meansbeing applied to said EXCLUSIVE OR gating means which delivers saidintermediate encoded digital pulses;

means for generating synchronized pulses which are synchronized withsaid intermediate encoded digital pulses, each synchronized pulse havinga time width duration which is less than and wholly contained within thetime width duration of the corresponding intermediate encoded digitalpulse;

second logic AND gating means for AND gating said intermediate encodeddigital and synchronized pulses and delivering a digital pulse trainoutput which is a function of said binary digits; and

means for receiving and filtering said digital pulse train output todeliver an analog signal.

3. A digital-to-analog converter system comprising means for generatingintermediate encoded digital pulses which are a function of binarydigits located in stored digital intelligence means;

means for generating synchronized pulses, which are synchronized withsaid intermediate encoded digital pulses, each synchronized pulse havinga time width duration which is less than and wholly contained within thetime width duration of the corresponding intermediate encoded digitalpulse;

means for logically AND gating said intermediate encoded digital andsynchronized pulses and delivering a digital pulse train output which isa function of said binary digits; and

means for receiving and filtering said digital pulse train output todeliver an analog signal, comprising analog switching means having onand off positions, weighted resistor network means, and filtermeans forgenerating intermediate encoded digital D pulses which are a function ofbinary digits located in stored digital intelligence means;

means for generating synchronized pulses, which are synchronized withsaid intermediate encoded digital pulses, each synchronized pulse havinga time width duration which is less than and wholly contained within thetime width duration of the corresponding intermediate encoded digitalpulse;

means for logically AND gating said intermediate en- 10 coded digitaland synchronized pulses and delivering a digital'pulse train outputwhich is a function of said binary digits; and

means for receiving and filtering said digital pulse train output todeliver an analog signal, comprising analog switching means having onand off positions, weighted resistor network means, and filtering means,said analog switching means being 7 adapted to be connected selectivelyto positive and negative voltage sources and to said' logic AND gatingmeans, the digital pulse train output providing selective actuation ofsaid analog switching means, the weighted resistor network being adaptedto be selectively energized by said voltage sources through said analogswitching means, said filtering means comprising operational amplifiermeans having a capacitor and a resistor connected in parallel in thefeedback path thereof, and being connected to said weighted resistornetwork to deliver said analog signal.

1. A digital to analog converter system comprising: commutator meansproviding interrogating pulses in a predetermined sequence; comparatormeans for comparing said interrogating pulses with binary digital datalocated in stored digital intelligence means to ascertain coincidence,and for delivering intermediate encoded digital pulses which are afunction of said binary digital data; synchronized counter means coupledwith said comparator means to enable synchronization; logic circuitrymeans adapted to receive the output of said synchronized circuit meansfor logic operations thereon to provide synchronized pulses which aresynchronized with said intermediate encoded digital pulses, eachsynchronized pulse having a time width duration which is less than andwholly contained within the time width duration of the correspondingintermediate encoded digital pulses; means for logically AND gating saidintermediate encoded digital and synchronized pulses and delivering adigital pulse train output which is a function of said binary digitaldata; analog switching means having on and off positions adapted to beselectively connected to positive or negative voltage sourcesrespectively, and operatively connected to said logic AND gating means,the digital pulse train output providing selective actuation of saidanalog switching means; weighted resistor network means connected tosaid analog switching means, and adapted to be selectively energized bysaid voltages through said analog switching means; operational amplifiermeans having a capacitor and a resistor connected in parallel in thefeedback path thereof, said operational amplifier means being coupled tosuch weighted resistor network means, the output of said operationalamplifier means delivering an analog signal.
 2. A digital-to-analogconverter system comprising: means for generating intermediate encodeddigital pulses which are a function of binary digits located in storeddigital intelligence means, comprising commutator means for providinginterrogating pulses in a predetermined ordered sequence; comparatormeans for comparing said interrogating pulses with said binary digits insaid stored digital intelligence means to ascertain coincidence,comprising first logic AND gating means, EXCLUSIVE OR gating means, saidfirst logic AND gating means having one input connected to said binarydigits and the other connected to receive said interrogating pulses, theoutputs of said first logic AND gating means being applied to saidEXCLUSIVE OR gating means which delivers said intermediate encodeddigital pulses; means for generating synchronized pulses which aresynchronized with said intermediate encoded digital pulses, eachsynchronized pulse having a time width duration which is less than andwholly contained within the time width duration of the correspondingintermediate encoded digital pulse; second logic AND gating means forAND gating said intermediate encoded digital and synchronized pulses anddelivering a digital pulse train output which is a function of saidbinary digits; and means for receiving and filtering said digital pulsetrain output to deliver an analog signal.
 3. A digital-to-analogconverter system comprising means for generating intermediate encodeddigital pulses which are a function of binary digits located in storeddigital intelligence means; means for generating synchronized pulses,which are synchronized with said intermediate encoded digital pulses,each synchronized pulse having a time width duration which is less thanand wholly contained within the time width duration of the correspondingintermediate encoded digital pulse; means for logically AND gating saidintermediate encoded digital and synchronized pulses and delivering adigital pulse train output which is a function of said binary digits;and means for receiving and filtering said digital pulse train output todeliver an analog signal, comprising analog switching means having onand off positions, weighted resistor network means, and filtering means,said analog switching means being adapted to be connected selectively topositive and negative voltage sources and to said second logic ANDgating means, the digital pulse train output providing selectiveactuation of said analog switching means, the weighted resistor networkbeing adapted to be selectively energized by said voltage sourcesthrough said analog switching means, said filtering means beingconnected to said weighted resistor network to deliver said analogsignal.
 4. A digital-to-analog converter system comprising means forgenerating intermediate encoded digital pulses which are a function ofbinary digits located in stored digital intelligence means; means forgenerating synchronized pulses, which are synchronized with saidintermediate encoded digital pulses, each synchronized pulse having atime width duration which is less than and wholly contained within thetime width duration of the corresponding intermediate encoded digitalpulse; means for logically AND gating said intermediate encoded digitaland synchronized pulses and delivering a digital pulse train outputwhich is a function of said binary digits; and means for receiving andfiltering said digital pulse train output to deliver an analog signal,comprising analog switching means having on and off positions, weightedresistor network means, and filtering means, said analog switching meansbeing adapted to be connected selectively to positive and negativevoltage sources and to said logic AND gating means, the digital pulsetrain output providing selective actuation of said analog switchingmeans, the weighted resistor network being adapted to be selectivelyenergized by said voltage sources through said analog switching means,said filtering means comprising operational amplifier means having acapacitor and a resistor connected in parallel in the feedback paththereof, and being connected to said weighted resistor network todeliver said analog signal.